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EL7158
Data Sheet May 14, 2007 FN7349.2
Ultra-High Current Pin Driver
The EL7158 high performance pin driver with three-state is suited to many ATE and level-shifting applications. The 12A peak drive capability makes this part an excellent choice when driving high capacitance loads. The output pin OUT is connected to input pins VH or VL respectively, depending on the status of the IN pin. When the OE pin is active low, the output is placed in the three-state mode. The isolation of the output FETs from the power supplies enables VH and VL to be set independently, enabling level-shifting to be implemented. Related to the EL7155, the EL7158 adds a lower supply pin VS- and makes VL an isolated and independent input. This feature adds applications flexibility and improves switching response due to the increased enhancement of the output FETs. This pin driver has improved performance over existing pin drivers. It is specifically designed to operate at voltages down to 0V across the switch elements while maintaining good speed and ON-resistance characteristics. Available in the 8 Ld SOIC package, the EL7158 is specified for operation over the full -40C to +85C temperature range.
Features
* Clocking speeds up to 40MHz * 12ns tR/tF at 2000pF CLOAD * 0.2ns rise and fall times mismatch * 0.5ns tON-tOFF prop delay mismatch * 3.5pF typical input capacitance * 12A peak drive * Low ON-resistance of 0.5 * High capacitive drive capability * Operates from 4.5V to 12V * Pb-free plus anneal available (RoHS compliant)
Applications
* ATE/burn-in testers * Level shifting * IGBT drivers * CCD drivers
Ordering Information
PART NUMBER EL7158IS EL7158IS-T7 PART MARKING 7158IS 7158IS 7158IS 7158ISZ 7158ISZ PACKAGE 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) TAPE & REEL 7" 13" 7" 13" PKG. DWG. # MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027
Pinout
EL7158 (8 LD SOIC) TOP VIEW
VS+ 1 OE 2 IN 3 GND 4 L O G I C 8 VH 7 OUT 6 VL 5 VS-
EL7158IS-T13 EL7158ISZ (Note) EL7158ISZ-T7 (Note)
EL7158ISZ-T13 7158ISZ (Note)
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003, 2004, 2007. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners.
EL7158
Absolute Maximum Ratings (TA = +25C)
Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.3V, VS +0.3V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA
Thermal Information
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Ambient operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see curves Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER INPUT VIH IIH VIL IIL CIN RIN OUTPUT ROVH ROVL IOUT IPK
VS+ = +12V, VH = +12V, VL = 0V, VS- = 0V, TA = +25C, unless otherwise specified. CONDITION MIN TYP MAX UNIT
DESCRIPTION
Logic `1' Input Voltage Logic `1' Input Current Logic `0' Input Voltage Logic `0' Input Current Input Capacitance Input Resistance VIL = 0V VIH = VS+
2.4 0.1 10 0.8 0.1 3.5 50 10
V A V A pF M
ON-Resistance VH to OUT ON-Resistance VL to OUT Output Leakage Current Peak Output Current (linear resistive operation) Continuous Output Current
IOUT = -500mA IOUT = +500mA OE = 0V, OUT = VH/VL Source Sink Source/Sink 500
0.5 0.5 0.1 12 12
1 1 10
A A A mA
IDC POWER SUPPLY IS IVH
Power Supply Current Off Leakage at VH and VL
Inputs = VS+ VH, VL = 0V
1.3 4
3 10
mA A
SWITCHING CHARACTERISTICS tR tF tRF td-1 td-2 td td-3 td-4 SR+ SRRise Time Fall Time tR, tF Mismatch Turn-Off Delay Time Turn-On Delay Time td-1-td-2 Mismatch Three-State Delay Enable Three-State Delay Disable VOUT+ Slew Rate VOUT- Slew Rate RLOAD = 6 RLOAD = 6 CL = 2000pF CL = 2000pF CL = 2000pF CL = 2000pF CL = 2000pF CL = 2000pF 12.0 12.2 0.2 22.5 22.0 0.5 22 22 800 800 ns ns ns ns ns ns ns ns V/s V/s
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FN7349.2 May 14, 2007
EL7158
Electrical Specifications
PARAMETER INPUT VIH IIH VIL IIL CIN RIN OUTPUT ROVH ROVL IOUT IPK ON-Resistance VH to OUT ON-Resistance VL to OUT Output Leakage Current Peak Output Current (linear resistive operation) Continuous Output Current IOUT = -500mA IOUT = +500mA OE = 0V, OUT = VH/VL Source Sink Source/Sink 500 0.5 0.5 0.1 1.2 1.2 1 1 10 A A A mA Logic `1' Input Voltage Logic `1' Input Current Logic `0' Input Voltage Logic `0' Input Current Input Capacitance Input Resistance VIL = 0V 0.1 3.5 50 VIH = VS+ 2.0 0.1 10 0.8 10 V A V A pF M VS+ = +12V, VH = +1.2V, VL = 0V, VS- = 0V, TA = +25C, unless otherwise specified. (Continued) CONDITION MIN TYP MAX UNIT
DESCRIPTION
IDC POWER SUPPLY IS VH
Power Supply Current Off Leakage at VH and VL
Inputs = VS+ VH, VL = 0V
1 4
2.5 10
mA A
SWITCHING CHARACTERISTICS tR tF tRF td-1 td-2 td td-3 td-4 SR+ SRRise Time Fall Time tR, tF Mismatch Turn-Off Delay Time Turn-On Delay Time td-1-td-2 Mismatch Three-State Delay Enable Three-State Delay Disable VOUT+ Slew Rate VOUT- Slew Rate RLOAD = 6 RLOAD = 6 CL = 2000pF CL = 2000pF CL = 2000pF CL = 2000pF CL = 2000pF CL = 2000pF 11 11 0 20.5 20.0 0.5 20 20 80 80 ns ns ns ns ns ns ns ns V/s V/s
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FN7349.2 May 14, 2007
EL7158 Typical Performance Curves
T = +25C 1.8 HIGH THRESHOLD INPUT VOLTAGE (V) 1.6 HYSTERESIS 1.4 SUPPLY CURRENT (mA) 2.0 T = +25C
1.6
1.2
ALL INPUTS = GND
0.8
1.2
LOW THRESHOLD
0.4 ALL INPUTS = VS+
1.0 5 10 SUPPLY VOLTAGE (V) 12
0 5 10 SUPPLY VOLTAGE (V) 12
FIGURE 1. INPUT THRESHOLD vs SUPPLY VOLTAGE
FIGURE 2. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE
IOUT = 500mA, T = +25C, VS+ = VH, VS- = VL = 0V 0.8 "ON" RESISTANCE ()
15
CL = 2000pF, T = +25C, VS+ = VH, VS- = VL = 0V
0.7
VH TO VOUT
RISE/FALL TIME (ns)
14 tR 13
0.6
0.5
VOUT TO VL
12
tF
0.4
5
7.5
10
12.5
11 5 6 7 8 9 10 11 12 SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FIGURE 3. "ON"-RESISTANCE vs SUPPLY VOLTAGE (VS+)
FIGURE 4. RISE/FALL TIME vs SUPPLY VOLTAGE
18
CL = 2000pF, VS+ = VH = 12V, VS- = VL = 0V
30
CL = 2000pF, T = +25C, VS+ = VH = 12V, VS- = VL = 0V
RISE/FALL TIME (ns)
16 DELAY TIME (ns) tR tr 14
28
26
td1
12
tR
24 td2 22
10
8 -50
20 0 50 TEMPERATURE (C) 100 150 5 6 7 8 9 10 11 12 SUPPLY VOLTAGE (V)
FIGURE 5. RISE/FALL TIME vs TEMPERATURE
FIGURE 6. PROPAGATION DELAY vs SUPPLY VOLTAGE
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FN7349.2 May 14, 2007
EL7158 Typical Performance Curves
(Continued)
26
CL = 2000pF, VS+ = VH = 12V, VS- = VL = 0V
70 60
VS+ = +12V, T = +25C
24 DELAY TIME (ns) tD1 22 tD2 20
RISE/FALL TIME (ns)
50 40 tF 30 20 10 tR
18 -50
-25
0
25
50
75
100
125
0 100
1k LOAD CAPACITANCE (pF)
10k
TEMPERATURE (C)
FIGURE 7. PROPAGATION DELAY vs TEMPERATURE
FIGURE 8. RISE/FALL TIME vs LOAD CAPACITANCE
5
VS+ = VH = 12V, VS- = VL = 0V, T = +25C, f = 20kHz
100
CL = 1000pF, T = +25C
4
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
10
VS+=12V
3
2
1.0 VS+=5V
VS+=10V
1
0 100
1k LOAD CAPACITANCE (pF)
10k
0.1 10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 9. SUPPLY CURRENT vs LOAD CAPACITANCE
FIGURE 10. SUPPLY CURRENT vs FREQUENCY
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.0 0.9 POWER DISSIPATION (W) 0.8 0.7 625mW 0.6 0.5 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C)
JA =
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.4 POWER DISSIPATION (W) 1.2 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) 909mW
SO IC 11 8 0 C/ W
SO 16
IC 8 C/ W
JA
=
0
FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 12. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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FN7349.2 May 14, 2007
EL7158
TABLE 1. TRUTH TABLE OE 0 0 1 1 IN 0 1 0 1 OUT Three-State Three-State VH VL TABLE 2. OPERATING VOLTAGE RANGE PIN VS- to GND VS+ to VSVH to VL VS+ to VH VS+ to GND VL to VSThree-State Output MIN -5 5 0 0 5 0 VL MAX 0 18 12 12 12 12 VH
5V INPUT 2.5V 0 90% 10% td1 tF td2 tR
INVERTED OUTPUT
FIGURE 13. TIMING DIAGRAM
VH VS+ VS+ 4.7F 10k 0.1F OE IN GND 1 2 3 4 EL7158 0.1F 4.7F VSL O G I C 8 OUT 7 6 5 0.1F 4.7F VL 2000pF 0.1F 4.7F
FIGURE 14. STANDARD TEST CONFIGURATION
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FN7349.2 May 14, 2007
EL7158 Pin Descriptions
PIN 1 2 NAME VS+ OE FUNCTION Positive Supply Voltage Output Enable
VS+
EQUIVALENT CIRCUIT
INPUT
VSCircuit 1
3 4 5 6 7
IN GND VSVL OUT
Input Ground Negative Supply Voltage Lower Output Voltage Output
Reference Circuit 1
VH
VSVS+ VOUT VSVSVL Circuit 2
8
VH
High Output Voltage
OE
VH
VS+
IN LEVEL SHIFTER GND
THREESTATE CONTROL
OUT
VSVL
FIGURE 15. BLOCK DIAGRAM
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FN7349.2 May 14, 2007
EL7158 Applications Information
Product Description
The EL7158 is a high performance 40MHz pin driver. It contains two analog switches connecting VH and VL to OUT. Depending on the value of the IN pin, one of the two switches will be closed and the other switch open. An output enable (OE) is also supplied which opens both switches simultaneously. Due to the topology of the EL7158, both the VH and VL pins can be connected to any voltage between the VS+ and VSpins, but VH must be greater than VL in order to prevent turning on the body diode at the output stage.
Power Dissipation Calculation
When switching at high speeds, or driving heavy loads, the EL7158 drive capability is limited by the rise in die temperature brought about by internal power dissipation. For reliable operation die temperature must be kept below TJMAX (+125C). It is necessary to calculate the power dissipation for a given application prior to selecting the package type. Power dissipation may be calculated:
PD = ( V S x I S ) + ( C INT x V S x f ) + ( C L x V OUT x f ) (EQ. 1)
2 2
Three-State Operation
When the OE pin is low, the output is three-state (floating). The output voltage is the parasitic capacitance's voltage. It can be any voltage between VH and VL, depending on the previous state. At three-state, the output voltage can be pushed to any voltage between VH and VL. The output voltage can't be pushed higher than VH or lower than VL since the body diode at the output stage will turn on.
where: VS is the total power supply to the EL7158 (from VS+ to GND) VOUT is the swing on the output (VH - VL) CL is the load capacitance CINT is the internal load capacitance (100pF max) IS is the quiescent supply current (3mA max) f is frequency Having obtained the application's power dissipation, a maximum package thermal coefficient may be determined, to maintain the internal die temperature below TJMAX:
T JMAX - T MAX JA = ---------------------------------------PD (EQ. 2)
Supply Voltage Range and Input Compatibility
The EL7158 is designed for operation on supplies from 5V to 18V (4.5V to 18V maximum). Table 2 shows the specifications for the relationship between the VS+, VS-, VH, VL, and GND pins. All input pins are compatible with both 3V and 5V CMOS signals. With a positive supply (VS+) of 5V, the EL7158 is also compatible with TTL inputs.
where: TJMAX is the maximum junction temperature (+125C) TMAX is the maximum operating temperature PD is the power dissipation calculated above JA thermal resistance on junction to ambient JA is 160C/W for the SOIC8 package when using a standard JEDEC JESD51-3 single-layer test board. If TJMAX is greater than +125C when calculated using Equation 2 , then one of the following actions must be taken: Reduce JA the system by designing more heat-sinking into the PCB (as compared to the standard JEDEC JESD51-3) De-rate the application either by reducing the switching frequency, the capacitive load, or the maximum operating (ambient) temperature (TMAX)
Power Supply Bypassing
When using the EL7158, it is very important to use adequate power supply bypassing. The high switching currents developed by the EL7158 necessitate the use of a bypass capacitor between the supplies (VS+ and VS-) and GND pins. It is recommended that a 2.2F tantalum capacitor be used in parallel with a 0.1F low-inductance ceramic MLC capacitor. These should be placed as close to the supply pins as possible. It is also recommended that the VH and VL pins have some level of bypassing, especially if the EL7158 is driving highly capacitive loads.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 8
FN7349.2 May 14, 2007
EL7158 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07
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FN7349.2 May 14, 2007

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